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0.35m 14-BIT 10MSPS ADC
BW1254X
GENERAL DESCRIPTION
BW1254X is a CMOS 14bit analog-to-digital converter (ADC). It converts the analog input signal into 14bit binary digital codes at a maximum sampling rate of 10MHz. The device is a monolithic ADC with an on-chip, high-performance, sample-and-hold Amplifier (SHA) and current reference and voltage reference. The structure allows both differential and single-ended input.
TYPICAL APPLICATIONS
-- Imaging (Copiers, Scanners, Cameras) -- Medical Instruments -- Digital Communication Systems -- uADSL System
FEATURES
-- Resolution : 14bit -- Maximum Conversion Rate : 10MHz -- Package Type : 48TSSOP -- Power Supply : 3.3V -- Power Consumption : 120mW (typical) -- Reference Voltage : Internal reference or 2V, 1V (dual reference) -- Input Range : 0.5V ~ 2.5V (2.0VP-P) -- Differential Linearity Error : 0.7 LSB -- Integral Linearity Error : 1.5 LSB -- Signal to Noise & Distortion Ratio : 72dB -- Total Harmonic Distortion : 80dB -- Out of Range Indicator -- Digital Output : CMOS Level -- Operating Temperature Range : 0C ~ 70C
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BW1254X
0.35m 14-BIT 10MSPS ADC
FUNCTIONAL BLOCK DIAGRAM
Analog Input
SHA
MDAC 1
MDAC 2
MDAC 3
FLASH 1 5
FLASH 2 4
FLASH 3 3
FLASH 4 3
Reference Output
Voltage Reference CLOCK GEN. DIGITAL LOGIC 14 Digital Output ORI
Clock
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0.35m 14-BIT 10MSPS ADC
BW1254X
CORE PIN DESCRIPTION
Name REFTOP REFBOT BGR CML CML1 VDDA1 VBBA1 VSSA1 AINT AINC ITEST STBY CKIN D[13:0] ORI VBBA2 VSSA2 VDDA2 I/O Type Abbr. -- AI: Analog Input -- DI: Digital Input -- AO: Analog Output -- DO: Digital Output -- AP: Analog Power -- AG: Analog Ground -- DP: Digital Power -- DG: Digital Ground -- AB: Analog Bidirectional -- DB: Digital Bidirectional I/O Type AB AB AB AB AB AP AG AG AI AI AB DI DI DO DO DG DG DP I/O Pad piar10_bb piar10_bb piar10_bb piar10_bb piar10_bb vdda vbba vssa piar10_bb piar10_bb pia_bb picc_bb picc_bb poa_bb poa_bb vbba vssd vddd Pin Description Reference Top Output/Force (2.0V) Reference Bottom Output/Force (1.0V) BGR output (1.23V) Internal Bias Internal Bias Analog Power (3.3V) Analog Sub Bias Analog Ground Analog Input + (Input Range : 1.0V ~ 2.0V) Analog Input (Input Range : 1.0V ~ 2.0V) open=use internal bias point VDD=power saving (standby), GND=normal Sampling Clock Input Digital Output Out of Range Indicator Digital Sub Bias Digital GND Digital Power (3.3V)
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BW1254X
0.35m 14-BIT 10MSPS ADC
CORE CONFIGURATION
VDDA1 VBBA1 VSSA2 VSSA1 VDDA2 VBBA2
AINT AINC
BW1254X
REFTOP REFBOT
[MSB:LSB] DO[13:0] OR I
BGR CML CML1 ITEST STBY CKIN
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0.35m 14-BIT 10MSPS ADC
BW1254X
ABSOLUTE MAXIMUM RATINGS
Characteristics Supply Voltage Analog Input Voltage Digital Input Voltage Storage Temperature Range Operating Temperature Range Symbol VDD AINT/AINC CLK Tstg Topr Value 4.5 VSS to VDD VSS to VDD -45 to 150 0 to 70 Unit V V V
C C
NOTE: 1. Absolute maximum rating specifies the values beyond which the device may be damaged permanently. Exposure to ABSOLUTE MAXIMUM RATING conditions for extended periods may affect reliability. Each condition value is applied with the other values kept within the following operating conditions and function operation under any of these conditions is not implied. 2. All voltages are measured with respect to VSS unless otherwise specified. 3. 100pF capacitor is discharged through a 1.5k resistor (Human body model)
OPERATING CONDITIONS Characteristics Supply Voltage Symbol VDDA1 VDDA2 VDDA3 AINT AINC Toper Min 3.15 Typ 3.3 Max 3.45 Unit V
Analog Input Voltage Operating Temperature
0.5 0
- 1.5 -
2.5 70
V C
NOTE: It is strongly recommended that all the supply pins (VDDA1, VDDA2, VDDA3) be powered from the same source to avoid power latch-up.
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BW1254X
0.35m 14-BIT 10MSPS ADC
DC ELECTRICAL CHARACTERISTICS
Characteristics Differential Nonlinearity Integral Nonlinearity Offset Voltage Symbol DNL Min - Typ 0.7 Max 1 Unit LSB Test Condition Internal Voltage Reference REFTOP=2V REFBOT=1V Internal Voltage Reference REFTOP=2V REFBOT=1V REFTOP=2V REFBOT=1V
INL
-
1.5
-
LSB
OFF
-
10
-
mV
NOTE: Converter Specifications : VDDA1=VDDA2=VDDA3=3.3V, VSSA1=VSSA2=VSSA3=0V, Toper=25C, REFTOP=2V, REFBOT=1V unless otherwise specified.
AC ELECTRICAL CHARACTERISTICS
Characteristics Maximum Conversion Rate Dynamic Supply Current Signal-to-Noise & Distortion Ratio Total Harmonic Distortion Symbol fc IVDD SNDR THD Min - - - - Typ 10 36 72 80 Max - - - - Unit MHz mA dB dB Test Condition AIN=AINT-AINC fc=10MHz (without system load) AIN=1MHz, Differential Input AIN=1MHz, Differential Input
NOTE: It is strongly recommended that all the supply pins (VDDA1, VDDA2, VDDA3) be powered from the same source to avoid power latch-up.
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0.35m 14-BIT 10MSPS ADC
BW1254X
I/O CHART
Index 0 1 2 ~ 2047 2048 2049 ~ 4093 4094 4095 AINT Input (V) ~ 0.00081 0.00081 ~ 0.00161 0.00161 ~ 0.00242 ~ 1.64919 ~ 1.65000 1.65000 ~ 1.65081 1.65081 ~ 1.65161 ~ 3.29758 ~ 3.29839 3.29839 ~ 3.29919 3.29919 ~ Digital Output 0000 0000 0000 0000 0000 0001 0000 0000 0010 ~ 0111 1111 1111 1000 0000 0000 1000 0000 0001 ~ 1111 1111 1101 1111 1111 1110 1111 1111 1111 1LSB=0.806mV VREF=3.3V AGND=0.0V
TIMING DIAGRAM
A1 AINT
A2 A5 Input Sampling Period
CKIN
DO[13:0]
D1
D2
D3
D4
D5
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BW1254X
0.35m 14-BIT 10MSPS ADC
FUNCTIONAL DESCRIPTION
1. The BW1254X is a CMOS four step pipelined Analog-to-Digital Converter. It contains 5-bit flash A/D Converters, 4bit, two 3bit flash A/D converters and three multiplying D/A Convertors. The N-bit flash ADC is composed of 2N-1 latched comparators, and multiplying DAC is composed of 2*(2N+1) capacitors and two fully-differential amplifiers. 2. The BW1254X operates as follows. During the first "L" cycle of external clock the analog input data is sampled, and the input is held from the rising edge of the external clock, which is fed to the first 5-bit flash ADC, and the first multiplying DAC. Multiplying DAC reconstructs a voltage corresponding to the first 5-bit ADC's output, and finally amplifies a residue voltage by 24. The second and third flash ADC, and MDAC are worked as same manner. Finally amplified residue voltage at the third multiplying DAC is fed to the last 3-bit flash ADC decides final 3-bit digital digital code. 3. BW1254X has the error correction scheme, which handles the output from mismatch in the first, second, third and fourth flash ADC.
MAIN BLOCK DESCRIPTION 1. SHA SHA (Sample-and-Hold Amplifier) is the circuit that samples the analog input signal and hold that value until next sample-time. It is good as small as its different value between analog input signal and output signal. SHA amp gain is higher than 70dB at 10MHz conversion rate, its settling-time must be shorten than 38ns with less than 1/2 LSB error voltage at 14bit resolution. This SHA is consist of fully differential op amp, switching tr. and sampling capacitor. The sampling clock is non-overlapping clock (Q1, Q2) and sampling capacitor value is about 4pF. SHA uses independent bias to protect interruption of any other circuit. SHA amp is designed that open-loop dc gain is higher than 70dB, phase margin is higher than 60 degrees. Its input block is designed to be the rail-to-rail architecture using complementary different pair. 2. FLASH The 5-bit flash converters compare analog signal (SAH output) with reference voltage, and that results transfer to MDAC and digital correction logic block. It is realized fully differential comparators of 31EA. Considering self-offset, dynamic feed through error, it should distinguish 40mV at least. First, the comparators charge the reference voltage at the sampling capacitors before transferred SHA output.That operation is performed on the phase of Q2, and discharging on the phase of Q1. That is, the comparators compare relative different values dual input voltage with dual reference voltage. Its output during Q1 operation is stored at the pre-latch block by Q1P. 3. MDAC MDAC is the most important block at this ADC and it decides the characteristics. MDAC is consist of two stage op amp, selection logic and capacitor array (c_array). c_array's compositions are the capacitors to charge the analog input and and the reference voltage, switches to control the path. Selection logic controls the c_array internal switches. If Q1 is high, selection's output are all low, the switches of tsw1 are off, the switches of tsw2 are all on. Therefore the capacitors of c_array can charge analog input values held at SHA.
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0.35m 14-BIT 10MSPS ADC
BW1254X
CORE EVALUATION GUIDE
1. ADC function is evaluated by external check on the bidirectional pads connected to input nodes of HOST DSP back-end circuit. 2. If User want the specific analog input range, the reference voltages may be forced.
VDDA1 VBBA1 VSSA2 VSSA1 VDDA2 VBBA2
AINT AINC DO[13:0] [MSB:LSB]
BW1254X
REFTOP REFBOT BGR CML CML1 ITEST ORI
STBY CKIN
D[13:0]
D[13:0 ] Digital Mux HOST DSP CORE D[13:0] Bidirectional PAD (ADC Function Test & externally forced Digital Input)
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BW1254X
0.35m 14-BIT 10MSPS ADC
PACKAGE CONFIGURATION
10u
0.1u
Digital I
1
10u 0.1u
BGR REFTOP REFBOT CML CML1 VDDA1 VDDA1 VBBA1 VSSA1 VSSA1 AINT NC AINC NC NC ITEST STBY VDDA3 VSSA3 NC NC NC NC NC
VDDA2 VDDA2 VSSA2 VSSA2 NC CKIN NC DO[13] DO[12]
48 47 46 45 43 42 41 40 39 50 0.1u 10u
2 3 4 5 6 7
10u
0.1u
10u
0.1u
10u
0.1u
VBBA2 44
10u
0.1u
8 9 10 11 12 13 14 15
DO[11] 38
BW1254X
DO[10] 37 DO[9] 36 DO[8] 35 DO[7] 34 DO[6] 33 DO[5] 32 DO[4] 31 DO[3] 30 DO[2] 29 DO[1] 28 DO[0] 27 ORI 26 TRIST 25
Analog Digital II
10u
0.1u
16 17 18
10u
0.1u
19 20 21 22 23 24
NOTE: NC denotes "No Connection".
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0.35m 14-BIT 10MSPS ADC
BW1254X
PACKAGE PIN DESCRIPTION
Pin No. 1 2 3 4 5 6, 7 8 9, 10 11 13 16 17 18 19 25 Name BGR REFTOP REFBOT CML CML1 VDDA1 VBBA1 VSSA1 AINT AINC ITEST STBY VDDA3 VSSA3 TRIST I/O Type AB AB AB AB AB AP AG AG AI AI AB DI PP PG DI Pin Description Reference Voltage Output Reference Top Output/Force Reference bottom Output/Force Internal Bias Internal Bias Analog Power (3.3V) Analog Sub Bias Analog Ground Analog Input + Analog Input open=use internal bias circuit VDDA=Power saving (Standby), GNP=Normal PAD Power (3.3V) PAD Ground Tri-state Buffer Input VDD=High Impedance, GND=Normal Out of Range Indicator Normal='Low' Out of Range='High' Digital Output (LSB) Digital Output Digital Output (MSB) Sampling Clock Input Digital Sub Bias Digital GND Digital Power (3.3V)
26
ORI
DO
27 28~39 40 42 44 45, 46 47, 48
DO[0] DO[1:12] DO[13] CKIN VBBA2 VSSA2 VDDA2
DO DO DO DI DG DG DP
NOTE: I/O TYPE PP and PG denote PAD Power and PAD Ground respectively.
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BW1254X
0.35m 14-BIT 10MSPS ADC
PACKAGE PIN DESCRIPTION (Continued)
Configuration
BGR REFTOP REFBOT CML CML1 VDDA1 VDDA1 VBBA1 VSSA1 VSSA1 AINT NC AINC NC NC ITEST STBY VDDA3 VSSA3 NC NC NC NC NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38
VDDA2 VDDA2 VSSA2 VSSA2 VBBA2 NC CKIN NC DO[13] DO[12] DO[11] DO[10] DO[9] DO[8] DO[7] DO[6] DO[5] DO[4] DO[3] DO[2] DO[1] DO[0] ORI TRIST
BW1254X
37 36 35 34 33 32 31 30 29 28 27 26 25
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0.35m 14-BIT 10MSPS ADC
BW1254X
USER GUIDE
1. Input Range -- If you want to using the single-ended input, you should use he input range as below. AINT: 0.5V ~ 2.5V, AINC: 1.5V. If you want to using the differential input, you should use the input range as below. AINT: 1.0V ~ 2.0V, AINC: 1.0V ~ 2.0V. AIN: AINT - AINC If you want to changing input range (AIN span), you can force reference voltages. AIN span = -REF ~ +REF REF = REFTOP - REFBOT
--
--
2. Power Consumption/Speed Optimization Yon can optimize the power consumption, as control the ITEST voltage level precisely . You can optimize the ADC's speed also, as control the ITEST voltage level.
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BW1254X
0.35m 14-BIT 10MSPS ADC
PHANTOM CELL INFORMATION
-- Pins of the core can be assigned externally (Package pins) or internally (internal ports) depending on design methods. The term "External" implies that the pins should be assigned externally like power pins. The term "External/internal" implies that the applications of these pins depend on the user.
VBBA
VSSA
VDDA
AINC
AINT
VBBA DO[0] ORI
VSSA DO[1]
VDDA DO[2] DO[3]
14bit 10MSPS ADC
ITEST DO[4] DO[5] DO[6]
BW1254X
REFBOT RETOP CML1 CML BGR STBY
CKIN VDDD VSSD VBBD
DO[10]
DO[11]
DO[12]
DO[13]
DO[7]
DO[8]
DO[9]
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0.35m 14-BIT 10MSPS ADC
BW1254X
PHANTOM CELL INFORMATION (Continued)
Pin Name VDDA VSSA VBBA VDDD VSSD VBBD AINT AINC CKIN REFTOP REFBOT CML CML1 BGR ITEST STBY ORI DO[13] DO[12] DO[11] DO[10] DO[9] DO[8] DO[7] DO[6] DO[5] DO[4] DO[3] DO[2] DO[1] DO[0] Pin Usage External External External External External External External/Internal External/Internal External/Internal External/Internal External/Internal External/Internal External/Internal External/Internal External/Internal External/Internal External/Internal External/Internal External/Internal External/Internal External/Internal External/Internal External/Internal External/Internal External/Internal External/Internal External/Internal External/Internal External/Internal External/Internal External/Internal - Separated from the analog clean signals if possible. - Do not exceed the length by 1,000um. - Separate from all other digital lines. - Separate from all other analog signals - Maintain the larger width and the shorter length as far as the pads. - Separate from all other digital lines. - Do not overlap with digtal lines. - Maintain the shotest path to pads. Pin Layout Guide - Maintain the large width of lines as far as the pads. - place the port positions to minimize the length of power lines. - Do not merge the analog powers with anoter power from other blocks. - Use good power and ground source on board.
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BW1254X
0.35m 14-BIT 10MSPS ADC
FEEDBACK REQUEST
It should be quite helpful to our ADC core development if you specify your system requirements on ADC in the following characteristic checking table and fill out the additional questions. We appreciate your interest in our products. Thank you very much. Characteristic Analog Power Supply Voltage Digital Power Supply Voltage Bit Resolution Reference Input Voltage Analog Input Voltage Operating Temperature Integral Non-linearity Error Differential Non-linearity Error Bottom Offset Voltage Error Top Offset Voltage Error Maximum Conversion Rate Dynamic Supply Current Power Dissipation Signal-to-noise Ratio Pipeline Delay Digital Output Format (Provide detailed description & timing diagram) 1. Between single input-output and differential input-output configurations, which one is suitable for your system and why? 2. Please comment on the internal/external pin configurations you want our ADC to have, if you have any reason to prefer some type of configuration. 3. Freely list those functions you want to be implemented in our ADC, if you have any. Min Typ Max Unit V V Bit V Vpp C LSB LSB mV mV MSPS mA mW dB CLK Remarks
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0.35m 14-BIT 10MSPS ADC
BW1254X
HISTORY CARD
Version ver 1.0 ver 1.1 Date 99.6. 02.4.16 Modified Items Original version published (formal) Phantom information added and the datasheet format changed Comments
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BW1254X
0.35m 14-BIT 10MSPS ADC
NOTES
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